reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
12698   { 8 /* adclb */, AArch64::ADCLB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12700   { 14 /* adclt */, AArch64::ADCLT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13530   { 984 /* eorbt */, AArch64::EORBT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13535   { 995 /* eortb */, AArch64::EORTB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17017   { 3928 /* saba */, AArch64::SABA_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17113   { 4088 /* sbclb */, AArch64::SBCLB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17115   { 4094 /* sbclt */, AArch64::SBCLT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17671   { 4808 /* sqrdmlah */, AArch64::SQRDMLAH_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17690   { 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19108   { 6120 /* tbx */, AArch64::TBX_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19172   { 6175 /* uaba */, AArch64::UABA_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20056   { 8 /* adclb */, AArch64::ADCLB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20058   { 14 /* adclt */, AArch64::ADCLT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20888   { 984 /* eorbt */, AArch64::EORBT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20893   { 995 /* eortb */, AArch64::EORTB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24375   { 3928 /* saba */, AArch64::SABA_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24471   { 4088 /* sbclb */, AArch64::SBCLB_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24473   { 4094 /* sbclt */, AArch64::SBCLT_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25029   { 4808 /* sqrdmlah */, AArch64::SQRDMLAH_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25048   { 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26466   { 6120 /* tbx */, AArch64::TBX_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26530   { 6175 /* uaba */, AArch64::UABA_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },