reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
14270   { 1473 /* fmlalb */, AArch64::FMLALB_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
14272   { 1480 /* fmlalt */, AArch64::FMLALT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
14301   { 1505 /* fmlslb */, AArch64::FMLSLB_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
14303   { 1512 /* fmlslt */, AArch64::FMLSLT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17348   { 4470 /* smlalb */, AArch64::SMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17353   { 4477 /* smlalt */, AArch64::SMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17368   { 4497 /* smlslb */, AArch64::SMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17373   { 4504 /* smlslt */, AArch64::SMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17524   { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17532   { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17549   { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
17557   { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
19419   { 6424 /* umlalb */, AArch64::UMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
19424   { 6431 /* umlalt */, AArch64::UMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
19439   { 6451 /* umlslb */, AArch64::UMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
19444   { 6458 /* umlslt */, AArch64::UMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
21628   { 1473 /* fmlalb */, AArch64::FMLALB_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
21630   { 1480 /* fmlalt */, AArch64::FMLALT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
21659   { 1505 /* fmlslb */, AArch64::FMLSLB_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
21661   { 1512 /* fmlslt */, AArch64::FMLSLT_ZZZI_SHH, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24706   { 4470 /* smlalb */, AArch64::SMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24711   { 4477 /* smlalt */, AArch64::SMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24726   { 4497 /* smlslb */, AArch64::SMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24731   { 4504 /* smlslt */, AArch64::SMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24882   { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24890   { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24907   { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
24915   { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
26777   { 6424 /* umlalb */, AArch64::UMLALB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
26782   { 6431 /* umlalt */, AArch64::UMLALT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
26797   { 6451 /* umlslb */, AArch64::UMLSLB_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },
26802   { 6458 /* umlslt */, AArch64::UMLSLT_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },