reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17002 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17228 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17757 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17772 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17836 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17851 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 19631 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 19680 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 24360 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 24586 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25115 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25130 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25194 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25209 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 26989 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 27038 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, },