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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12718 { 25 /* add */, AArch64::ADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12816 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12897 { 269 /* bdep */, AArch64::BDEP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12901 { 274 /* bext */, AArch64::BEXT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12907 { 283 /* bgrp */, AArch64::BGRP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12924 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13509 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13620 { 1072 /* fadd */, AArch64::FADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14350 { 1535 /* fmul */, AArch64::FMUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14440 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14565 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14590 { 1730 /* fsub */, AArch64::FSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14613 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
14616 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
16678 { 3410 /* mul */, AArch64::MUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
16788 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17265 { 4404 /* sm4ekey */, AArch64::SM4EKEY_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2SM4, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17384 { 4530 /* smulh */, AArch64::SMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17442 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17562 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17709 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17860 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
18955 { 5924 /* sub */, AArch64::SUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19079 { 6111 /* tbl */, AArch64::TBL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19137 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19152 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19454 { 6484 /* umulh */, AArch64::UMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19489 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19689 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19893 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19908 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20014 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20029 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20076 { 25 /* add */, AArch64::ADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20174 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20255 { 269 /* bdep */, AArch64::BDEP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20259 { 274 /* bext */, AArch64::BEXT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20265 { 283 /* bgrp */, AArch64::BGRP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20282 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20867 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20978 { 1072 /* fadd */, AArch64::FADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21708 { 1535 /* fmul */, AArch64::FMUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21798 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21923 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21948 { 1730 /* fsub */, AArch64::FSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21971 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21974 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24036 { 3410 /* mul */, AArch64::MUL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24146 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24624 { 4404 /* sm4ekey */, AArch64::SM4EKEY_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2SM4, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24742 { 4530 /* smulh */, AArch64::SMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24800 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24920 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25067 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25218 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26313 { 5924 /* sub */, AArch64::SUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26437 { 6111 /* tbl */, AArch64::TBL_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26495 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26510 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26812 { 6484 /* umulh */, AArch64::UMULH_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26847 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27047 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27251 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27266 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27372 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27387 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },