reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17055   { 3978 /* sabdlb */, AArch64::SABDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17058   { 3985 /* sabdlt */, AArch64::SABDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17076   { 4012 /* saddlb */, AArch64::SADDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17079   { 4019 /* saddlbt */, AArch64::SADDLBT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17088   { 4034 /* saddlt */, AArch64::SADDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17403   { 4549 /* smullb */, AArch64::SMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17408   { 4556 /* smullt */, AArch64::SMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17591   { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17596   { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
18020   { 5177 /* ssublb */, AArch64::SSUBLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
18023   { 5184 /* ssublbt */, AArch64::SSUBLBT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
18026   { 5192 /* ssublt */, AArch64::SSUBLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
18029   { 5199 /* ssubltb */, AArch64::SSUBLTB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19210   { 6225 /* uabdlb */, AArch64::UABDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19213   { 6232 /* uabdlt */, AArch64::UABDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19231   { 6259 /* uaddlb */, AArch64::UADDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19240   { 6273 /* uaddlt */, AArch64::UADDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19473   { 6503 /* umullb */, AArch64::UMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19478   { 6510 /* umullt */, AArch64::UMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19842   { 6836 /* usublb */, AArch64::USUBLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19845   { 6843 /* usublt */, AArch64::USUBLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24413   { 3978 /* sabdlb */, AArch64::SABDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24416   { 3985 /* sabdlt */, AArch64::SABDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24434   { 4012 /* saddlb */, AArch64::SADDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24437   { 4019 /* saddlbt */, AArch64::SADDLBT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24446   { 4034 /* saddlt */, AArch64::SADDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24761   { 4549 /* smullb */, AArch64::SMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24766   { 4556 /* smullt */, AArch64::SMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24949   { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24954   { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25378   { 5177 /* ssublb */, AArch64::SSUBLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25381   { 5184 /* ssublbt */, AArch64::SSUBLBT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25384   { 5192 /* ssublt */, AArch64::SSUBLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25387   { 5199 /* ssubltb */, AArch64::SSUBLTB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26568   { 6225 /* uabdlb */, AArch64::UABDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26571   { 6232 /* uabdlt */, AArch64::UABDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26589   { 6259 /* uaddlb */, AArch64::UADDLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26598   { 6273 /* uaddlt */, AArch64::UADDLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26831   { 6503 /* umullb */, AArch64::UMULLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26836   { 6510 /* umullt */, AArch64::UMULLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27200   { 6836 /* usublb */, AArch64::USUBLB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27203   { 6843 /* usublt */, AArch64::USUBLT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },