reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17405 { 4549 /* smullb */, AArch64::SMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 17410 { 4556 /* smullt */, AArch64::SMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 17593 { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 17598 { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 19475 { 6503 /* umullb */, AArch64::UMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 19480 { 6510 /* umullt */, AArch64::UMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 24763 { 4549 /* smullb */, AArch64::SMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 24768 { 4556 /* smullt */, AArch64::SMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 24951 { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 24956 { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 26833 { 6503 /* umullb */, AArch64::UMULLB_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, }, 26838 { 6510 /* umullt */, AArch64::UMULLT_ZZZI_S, Convert__SVEVectorSReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorHReg, MCK_SVEVector3bHReg, MCK_IndexRange0_7 }, },