reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
16999 { 3883 /* rshrnb */, AArch64::RSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17225 { 4311 /* shrnb */, AArch64::SHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17754 { 4867 /* sqrshrnb */, AArch64::SQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17769 { 4904 /* sqrshrunb */, AArch64::SQRSHRUNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17833 { 4959 /* sqshrnb */, AArch64::SQSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 17848 { 4992 /* sqshrunb */, AArch64::SQSHRUNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 19628 { 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 19677 { 6671 /* uqshrnb */, AArch64::UQSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 24357 { 3883 /* rshrnb */, AArch64::RSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 24583 { 4311 /* shrnb */, AArch64::SHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25112 { 4867 /* sqrshrnb */, AArch64::SQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25127 { 4904 /* sqrshrunb */, AArch64::SQRSHRUNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25191 { 4959 /* sqshrnb */, AArch64::SQSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 25206 { 4992 /* sqshrunb */, AArch64::SQSHRUNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 26986 { 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, }, 27035 { 6671 /* uqshrnb */, AArch64::UQSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorDReg, MCK_Imm1_32 }, },