reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
16431 { 3300 /* lsl */, AArch64::LSL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 17798 { 4924 /* sqshl */, AArch64::SQSHL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 17820 { 4937 /* sqshlu */, AArch64::SQSHLU_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 19657 { 6643 /* uqshl */, AArch64::UQSHL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 23789 { 3300 /* lsl */, AArch64::LSL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 25156 { 4924 /* sqshl */, AArch64::SQSHL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 25178 { 4937 /* sqshlu */, AArch64::SQSHLU_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, }, 27015 { 6643 /* uqshl */, AArch64::UQSHL_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_Imm0_31 }, },