reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
14113 { 1364 /* fmad */, AArch64::FMAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14254 { 1455 /* fmla */, AArch64::FMLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14285 { 1487 /* fmls */, AArch64::FMLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14341 { 1524 /* fmsb */, AArch64::FMSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14405 { 1551 /* fnmad */, AArch64::FNMAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14411 { 1564 /* fnmla */, AArch64::FNMLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14414 { 1570 /* fnmls */, AArch64::FNMLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 14417 { 1576 /* fnmsb */, AArch64::FNMSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 16474 { 3328 /* mad */, AArch64::MAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 16491 { 3343 /* mla */, AArch64::MLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 16508 { 3347 /* mls */, AArch64::MLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 16665 { 3397 /* msb */, AArch64::MSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21471 { 1364 /* fmad */, AArch64::FMAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21617 { 1455 /* fmla */, AArch64::FMLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21648 { 1487 /* fmls */, AArch64::FMLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21699 { 1524 /* fmsb */, AArch64::FMSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21763 { 1551 /* fnmad */, AArch64::FNMAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21769 { 1564 /* fnmla */, AArch64::FNMLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21772 { 1570 /* fnmls */, AArch64::FNMLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 21775 { 1576 /* fnmsb */, AArch64::FNMSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 23832 { 3328 /* mad */, AArch64::MAD_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 23853 { 3343 /* mla */, AArch64::MLA_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 23870 { 3347 /* mls */, AArch64::MLS_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, }, 24023 { 3397 /* msb */, AArch64::MSB_ZPmZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },