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definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
16069   { 2588 /* ldnt1b */, AArch64::LDNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
16094   { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
16105   { 2609 /* ldnt1sb */, AArch64::LDNT1SB_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
16113   { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
16128   { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23427   { 2588 /* ldnt1b */, AArch64::LDNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23452   { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23463   { 2609 /* ldnt1sb */, AArch64::LDNT1SB_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23471   { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23486   { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },