reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
14984   { 1863 /* ld1d */, AArch64::GLD1D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15026   { 1868 /* ld1h */, AArch64::GLD1H_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15240   { 1957 /* ld1sh */, AArch64::GLD1SH_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15264   { 1963 /* ld1sw */, AArch64::GLD1SW_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15302   { 1969 /* ld1w */, AArch64::GLD1W_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15818   { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15858   { 2464 /* ldff1h */, AArch64::GLDFF1H_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15924   { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15944   { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
15980   { 2495 /* ldff1w */, AArch64::GLDFF1W_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
22342   { 1863 /* ld1d */, AArch64::GLD1D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
22384   { 1868 /* ld1h */, AArch64::GLD1H_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
22598   { 1957 /* ld1sh */, AArch64::GLD1SH_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
22622   { 1963 /* ld1sw */, AArch64::GLD1SW_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
22660   { 1969 /* ld1w */, AArch64::GLD1W_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
23176   { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
23216   { 2464 /* ldff1h */, AArch64::GLDFF1H_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
23282   { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
23302   { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },
23338   { 2495 /* ldff1w */, AArch64::GLDFF1W_D_UXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },