reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
14982   { 1863 /* ld1d */, AArch64::GLD1D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15024   { 1868 /* ld1h */, AArch64::GLD1H_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15238   { 1957 /* ld1sh */, AArch64::GLD1SH_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15262   { 1963 /* ld1sw */, AArch64::GLD1SW_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15300   { 1969 /* ld1w */, AArch64::GLD1W_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15816   { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15856   { 2464 /* ldff1h */, AArch64::GLDFF1H_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15922   { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15942   { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
15978   { 2495 /* ldff1w */, AArch64::GLDFF1W_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
22340   { 1863 /* ld1d */, AArch64::GLD1D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
22382   { 1868 /* ld1h */, AArch64::GLD1H_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
22596   { 1957 /* ld1sh */, AArch64::GLD1SH_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
22620   { 1963 /* ld1sw */, AArch64::GLD1SW_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
22658   { 1969 /* ld1w */, AArch64::GLD1W_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
23174   { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
23214   { 2464 /* ldff1h */, AArch64::GLDFF1H_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
23280   { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
23300   { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },
23336   { 2495 /* ldff1w */, AArch64::GLDFF1W_D_SXTW_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW648, MCK__93_ }, },