reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17001 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 17227 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 17756 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 17771 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 17835 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 17850 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 19630 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 19679 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 24359 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 24585 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 25114 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 25129 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 25193 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 25208 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 26988 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, }, 27037 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg1_1__Imm1_161_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorSReg, MCK_Imm1_16 }, },