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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12716 { 25 /* add */, AArch64::ADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12814 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12896 { 269 /* bdep */, AArch64::BDEP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12900 { 274 /* bext */, AArch64::BEXT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12906 { 283 /* bgrp */, AArch64::BGRP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12922 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
13507 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
13619 { 1072 /* fadd */, AArch64::FADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14349 { 1535 /* fmul */, AArch64::FMUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14439 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14564 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14589 { 1730 /* fsub */, AArch64::FSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14612 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
14615 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
16676 { 3410 /* mul */, AArch64::MUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
16786 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17383 { 4530 /* smulh */, AArch64::SMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17440 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17561 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17708 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
17858 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
18953 { 5924 /* sub */, AArch64::SUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19076 { 6111 /* tbl */, AArch64::TBL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19136 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19151 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19453 { 6484 /* umulh */, AArch64::UMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19487 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19687 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19892 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
19907 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20013 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20028 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20074 { 25 /* add */, AArch64::ADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20172 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20254 { 269 /* bdep */, AArch64::BDEP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20258 { 274 /* bext */, AArch64::BEXT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20264 { 283 /* bgrp */, AArch64::BGRP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20280 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20865 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20977 { 1072 /* fadd */, AArch64::FADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21707 { 1535 /* fmul */, AArch64::FMUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21797 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21922 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21947 { 1730 /* fsub */, AArch64::FSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21970 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
21973 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24034 { 3410 /* mul */, AArch64::MUL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24144 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24741 { 4530 /* smulh */, AArch64::SMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24798 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
24919 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25066 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
25216 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26311 { 5924 /* sub */, AArch64::SUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26434 { 6111 /* tbl */, AArch64::TBL_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26494 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26509 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26811 { 6484 /* umulh */, AArch64::UMULH_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
26845 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27045 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27250 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27265 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27371 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
27386 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },