reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17104   { 4067 /* saddwb */, AArch64::SADDWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
17107   { 4074 /* saddwt */, AArch64::SADDWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
18037   { 5220 /* ssubwb */, AArch64::SSUBWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
18040   { 5227 /* ssubwt */, AArch64::SSUBWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
19257   { 6306 /* uaddwb */, AArch64::UADDWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
19260   { 6313 /* uaddwt */, AArch64::UADDWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
19853   { 6863 /* usubwb */, AArch64::USUBWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
19856   { 6870 /* usubwt */, AArch64::USUBWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
24462   { 4067 /* saddwb */, AArch64::SADDWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
24465   { 4074 /* saddwt */, AArch64::SADDWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
25395   { 5220 /* ssubwb */, AArch64::SSUBWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
25398   { 5227 /* ssubwt */, AArch64::SSUBWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
26615   { 6306 /* uaddwb */, AArch64::UADDWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
26618   { 6313 /* uaddwt */, AArch64::UADDWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
27211   { 6863 /* usubwb */, AArch64::USUBWB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },
27214   { 6870 /* usubwt */, AArch64::USUBWT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorBReg }, },