reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12893 { 264 /* bcax */, AArch64::BCAX_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 12978 { 426 /* bsl */, AArch64::BSL_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 12981 { 430 /* bsl1n */, AArch64::BSL1N_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 12982 { 436 /* bsl2n */, AArch64::BSL2N_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 13526 { 979 /* eor3 */, AArch64::EOR3_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16722 { 3434 /* nbsl */, AArch64::NBSL_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20252 { 264 /* bcax */, AArch64::BCAX_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20338 { 426 /* bsl */, AArch64::BSL_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20339 { 430 /* bsl1n */, AArch64::BSL1N_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20340 { 436 /* bsl2n */, AArch64::BSL2N_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20885 { 979 /* eor3 */, AArch64::EOR3_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 24080 { 3434 /* nbsl */, AArch64::NBSL_ZZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__SVEVectorDReg1_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },