reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12719 { 25 /* add */, AArch64::ADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 17443 { 4576 /* sqadd */, AArch64::SQADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 17861 { 5010 /* sqsub */, AArch64::SQSUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 18956 { 5924 /* sub */, AArch64::SUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 18993 { 5971 /* subr */, AArch64::SUBR_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 19490 { 6517 /* uqadd */, AArch64::UQADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 19690 { 6687 /* uqsub */, AArch64::UQSUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 20077 { 25 /* add */, AArch64::ADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 24801 { 4576 /* sqadd */, AArch64::SQADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 25219 { 5010 /* sqsub */, AArch64::SQSUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 26314 { 5924 /* sub */, AArch64::SUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 26351 { 5971 /* subr */, AArch64::SUBR_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 26848 { 6517 /* uqadd */, AArch64::UQADD_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, }, 27048 { 6687 /* uqsub */, AArch64::UQSUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEAddSubImm64 }, },