reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17034   { 3946 /* sabalb */, AArch64::SABALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17037   { 3953 /* sabalt */, AArch64::SABALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17347   { 4470 /* smlalb */, AArch64::SMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17352   { 4477 /* smlalt */, AArch64::SMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17367   { 4497 /* smlslb */, AArch64::SMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17372   { 4504 /* smlslt */, AArch64::SMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17523   { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17528   { 4650 /* sqdmlalbt */, AArch64::SQDMLALBT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17531   { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17548   { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17553   { 4695 /* sqdmlslbt */, AArch64::SQDMLSLBT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17556   { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19189   { 6193 /* uabalb */, AArch64::UABALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19192   { 6200 /* uabalt */, AArch64::UABALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19418   { 6424 /* umlalb */, AArch64::UMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19423   { 6431 /* umlalt */, AArch64::UMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19438   { 6451 /* umlslb */, AArch64::UMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19443   { 6458 /* umlslt */, AArch64::UMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24392   { 3946 /* sabalb */, AArch64::SABALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24395   { 3953 /* sabalt */, AArch64::SABALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24705   { 4470 /* smlalb */, AArch64::SMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24710   { 4477 /* smlalt */, AArch64::SMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24725   { 4497 /* smlslb */, AArch64::SMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24730   { 4504 /* smlslt */, AArch64::SMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24881   { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24886   { 4650 /* sqdmlalbt */, AArch64::SQDMLALBT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24889   { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24906   { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24911   { 4695 /* sqdmlslbt */, AArch64::SQDMLSLBT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24914   { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26547   { 6193 /* uabalb */, AArch64::UABALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26550   { 6200 /* uabalt */, AArch64::UABALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26776   { 6424 /* umlalb */, AArch64::UMLALB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26781   { 6431 /* umlalt */, AArch64::UMLALT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26796   { 6451 /* umlslb */, AArch64::UMLSLB_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26801   { 6458 /* umlslt */, AArch64::UMLSLT_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },