reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17349 { 4470 /* smlalb */, AArch64::SMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17354 { 4477 /* smlalt */, AArch64::SMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17369 { 4497 /* smlslb */, AArch64::SMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17374 { 4504 /* smlslt */, AArch64::SMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17525 { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17533 { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17550 { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17558 { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19420 { 6424 /* umlalb */, AArch64::UMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19425 { 6431 /* umlalt */, AArch64::UMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19440 { 6451 /* umlslb */, AArch64::UMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19445 { 6458 /* umlslt */, AArch64::UMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24707 { 4470 /* smlalb */, AArch64::SMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24712 { 4477 /* smlalt */, AArch64::SMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24727 { 4497 /* smlslb */, AArch64::SMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24732 { 4504 /* smlslt */, AArch64::SMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24883 { 4641 /* sqdmlalb */, AArch64::SQDMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24891 { 4660 /* sqdmlalt */, AArch64::SQDMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24908 { 4686 /* sqdmlslb */, AArch64::SQDMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24916 { 4705 /* sqdmlslt */, AArch64::SQDMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26778 { 6424 /* umlalb */, AArch64::UMLALB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26783 { 6431 /* umlalt */, AArch64::UMLALT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26798 { 6451 /* umlslb */, AArch64::UMLSLB_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26803 { 6458 /* umlslt */, AArch64::UMLSLT_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, },