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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12694 { 0 /* abs */, AArch64::ABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
13070 { 603 /* cls */, AArch64::CLS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
13082 { 607 /* clz */, AArch64::CLZ_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
13351 { 745 /* cnot */, AArch64::CNOT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
13357 { 750 /* cnt */, AArch64::CNT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
13573 { 1043 /* fabs */, AArch64::FABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14052 { 1314 /* fcvtzs */, AArch64::FCVTZS_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14087 { 1321 /* fcvtzu */, AArch64::FCVTZU_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14111 { 1358 /* flogb */, AArch64::FLOGB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14403 { 1546 /* fneg */, AArch64::FNEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14452 { 1609 /* frecpx */, AArch64::FRECPX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14483 { 1652 /* frinta */, AArch64::FRINTA_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14494 { 1659 /* frinti */, AArch64::FRINTI_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14505 { 1666 /* frintm */, AArch64::FRINTM_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14516 { 1673 /* frintn */, AArch64::FRINTN_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14527 { 1680 /* frintp */, AArch64::FRINTP_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14538 { 1687 /* frintx */, AArch64::FRINTX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14549 { 1694 /* frintz */, AArch64::FRINTZ_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
14585 { 1724 /* fsqrt */, AArch64::FSQRT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16647 { 3375 /* movprfx */, AArch64::MOVPRFX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16737 { 3439 /* neg */, AArch64::NEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16757 { 3477 /* not */, AArch64::NOT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16943 { 3780 /* rbit */, AArch64::RBIT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16981 { 3841 /* revb */, AArch64::REVB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16983 { 3846 /* revh */, AArch64::REVH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
16984 { 3851 /* revw */, AArch64::REVW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
17155 { 4110 /* scvtf */, AArch64::SCVTF_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
17433 { 4570 /* sqabs */, AArch64::SQABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
17660 { 4792 /* sqneg */, AArch64::SQNEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19054 { 6076 /* sxtb */, AArch64::SXTB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19058 { 6081 /* sxth */, AArch64::SXTH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19072 { 6097 /* sxtw */, AArch64::SXTW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19299 { 6325 /* ucvtf */, AArch64::UCVTF_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19869 { 6893 /* uxtb */, AArch64::UXTB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19873 { 6898 /* uxth */, AArch64::UXTH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
19887 { 6914 /* uxtw */, AArch64::UXTW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20052 { 0 /* abs */, AArch64::ABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20428 { 603 /* cls */, AArch64::CLS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20440 { 607 /* clz */, AArch64::CLZ_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20709 { 745 /* cnot */, AArch64::CNOT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20715 { 750 /* cnt */, AArch64::CNT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
20931 { 1043 /* fabs */, AArch64::FABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21410 { 1314 /* fcvtzs */, AArch64::FCVTZS_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21445 { 1321 /* fcvtzu */, AArch64::FCVTZU_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21469 { 1358 /* flogb */, AArch64::FLOGB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21761 { 1546 /* fneg */, AArch64::FNEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21810 { 1609 /* frecpx */, AArch64::FRECPX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21841 { 1652 /* frinta */, AArch64::FRINTA_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21852 { 1659 /* frinti */, AArch64::FRINTI_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21863 { 1666 /* frintm */, AArch64::FRINTM_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21874 { 1673 /* frintn */, AArch64::FRINTN_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21885 { 1680 /* frintp */, AArch64::FRINTP_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21896 { 1687 /* frintx */, AArch64::FRINTX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21907 { 1694 /* frintz */, AArch64::FRINTZ_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
21943 { 1724 /* fsqrt */, AArch64::FSQRT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24005 { 3375 /* movprfx */, AArch64::MOVPRFX_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24095 { 3439 /* neg */, AArch64::NEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24115 { 3477 /* not */, AArch64::NOT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24301 { 3780 /* rbit */, AArch64::RBIT_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24339 { 3841 /* revb */, AArch64::REVB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24341 { 3846 /* revh */, AArch64::REVH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24342 { 3851 /* revw */, AArch64::REVW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24513 { 4110 /* scvtf */, AArch64::SCVTF_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
24791 { 4570 /* sqabs */, AArch64::SQABS_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
25018 { 4792 /* sqneg */, AArch64::SQNEG_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
26412 { 6076 /* sxtb */, AArch64::SXTB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
26416 { 6081 /* sxth */, AArch64::SXTH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
26430 { 6097 /* sxtw */, AArch64::SXTW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
26657 { 6325 /* ucvtf */, AArch64::UCVTF_ZPmZ_DtoD, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
27227 { 6893 /* uxtb */, AArch64::UXTB_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
27231 { 6898 /* uxth */, AArch64::UXTH_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },
27245 { 6914 /* uxtw */, AArch64::UXTW_ZPmZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg }, },