reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
16838   { 3648 /* pmullb */, AArch64::PMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
16841   { 3655 /* pmullt */, AArch64::PMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17056   { 3978 /* sabdlb */, AArch64::SABDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17059   { 3985 /* sabdlt */, AArch64::SABDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17077   { 4012 /* saddlb */, AArch64::SADDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17080   { 4019 /* saddlbt */, AArch64::SADDLBT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17089   { 4034 /* saddlt */, AArch64::SADDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17404   { 4549 /* smullb */, AArch64::SMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17409   { 4556 /* smullt */, AArch64::SMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17592   { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
17597   { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
18021   { 5177 /* ssublb */, AArch64::SSUBLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
18024   { 5184 /* ssublbt */, AArch64::SSUBLBT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
18027   { 5192 /* ssublt */, AArch64::SSUBLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
18030   { 5199 /* ssubltb */, AArch64::SSUBLTB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19211   { 6225 /* uabdlb */, AArch64::UABDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19214   { 6232 /* uabdlt */, AArch64::UABDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19232   { 6259 /* uaddlb */, AArch64::UADDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19241   { 6273 /* uaddlt */, AArch64::UADDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19474   { 6503 /* umullb */, AArch64::UMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19479   { 6510 /* umullt */, AArch64::UMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19843   { 6836 /* usublb */, AArch64::USUBLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
19846   { 6843 /* usublt */, AArch64::USUBLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24196   { 3648 /* pmullb */, AArch64::PMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24199   { 3655 /* pmullt */, AArch64::PMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24414   { 3978 /* sabdlb */, AArch64::SABDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24417   { 3985 /* sabdlt */, AArch64::SABDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24435   { 4012 /* saddlb */, AArch64::SADDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24438   { 4019 /* saddlbt */, AArch64::SADDLBT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24447   { 4034 /* saddlt */, AArch64::SADDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24762   { 4549 /* smullb */, AArch64::SMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24767   { 4556 /* smullt */, AArch64::SMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24950   { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
24955   { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25379   { 5177 /* ssublb */, AArch64::SSUBLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25382   { 5184 /* ssublbt */, AArch64::SSUBLBT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25385   { 5192 /* ssublt */, AArch64::SSUBLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
25388   { 5199 /* ssubltb */, AArch64::SSUBLTB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26569   { 6225 /* uabdlb */, AArch64::UABDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26572   { 6232 /* uabdlt */, AArch64::UABDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26590   { 6259 /* uaddlb */, AArch64::UADDLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26599   { 6273 /* uaddlt */, AArch64::UADDLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26832   { 6503 /* umullb */, AArch64::UMULLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
26837   { 6510 /* umullt */, AArch64::UMULLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27201   { 6836 /* usublb */, AArch64::USUBLB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
27204   { 6843 /* usublt */, AArch64::USUBLT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },