reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17406 { 4549 /* smullb */, AArch64::SMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17411 { 4556 /* smullt */, AArch64::SMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17594 { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 17599 { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19476 { 6503 /* umullb */, AArch64::UMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 19481 { 6510 /* umullt */, AArch64::UMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24764 { 4549 /* smullb */, AArch64::SMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24769 { 4556 /* smullt */, AArch64::SMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24952 { 4739 /* sqdmullb */, AArch64::SQDMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 24957 { 4748 /* sqdmullt */, AArch64::SQDMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26834 { 6503 /* umullb */, AArch64::UMULLB_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, }, 26839 { 6510 /* umullt */, AArch64::UMULLT_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_31_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorSReg, MCK_SVEVector4bSReg, MCK_IndexRange0_3 }, },