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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12720 { 25 /* add */, AArch64::ADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12819 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12898 { 269 /* bdep */, AArch64::BDEP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12902 { 274 /* bext */, AArch64::BEXT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12908 { 283 /* bgrp */, AArch64::BGRP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12927 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13512 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13621 { 1072 /* fadd */, AArch64::FADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14351 { 1535 /* fmul */, AArch64::FMUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14441 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14566 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14591 { 1730 /* fsub */, AArch64::FSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14614 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
14617 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
16680 { 3410 /* mul */, AArch64::MUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
16791 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
16935 { 3775 /* rax1 */, AArch64::RAX1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2SHA3, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
17385 { 4530 /* smulh */, AArch64::SMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
17444 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
17563 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
17710 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
17862 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
18957 { 5924 /* sub */, AArch64::SUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19082 { 6111 /* tbl */, AArch64::TBL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19138 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19153 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19455 { 6484 /* umulh */, AArch64::UMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19491 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19691 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19894 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
19909 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20015 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20030 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20078 { 25 /* add */, AArch64::ADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20177 { 120 /* and */, AArch64::AND_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20256 { 269 /* bdep */, AArch64::BDEP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20260 { 274 /* bext */, AArch64::BEXT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20266 { 283 /* bgrp */, AArch64::BGRP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20285 { 288 /* bic */, AArch64::BIC_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20870 { 975 /* eor */, AArch64::EOR_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20979 { 1072 /* fadd */, AArch64::FADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21709 { 1535 /* fmul */, AArch64::FMUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21799 { 1602 /* frecps */, AArch64::FRECPS_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21924 { 1709 /* frsqrts */, AArch64::FRSQRTS_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21949 { 1730 /* fsub */, AArch64::FSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21972 { 1747 /* ftsmul */, AArch64::FTSMUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21975 { 1754 /* ftssel */, AArch64::FTSSEL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24038 { 3410 /* mul */, AArch64::MUL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24149 { 3495 /* orr */, AArch64::ORR_ZZZ, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24294 { 3775 /* rax1 */, AArch64::RAX1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2SHA3, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24743 { 4530 /* smulh */, AArch64::SMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24802 { 4576 /* sqadd */, AArch64::SQADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
24921 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
25068 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
25220 { 5010 /* sqsub */, AArch64::SQSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26315 { 5924 /* sub */, AArch64::SUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26440 { 6111 /* tbl */, AArch64::TBL_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26496 { 6144 /* trn1 */, AArch64::TRN1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26511 { 6149 /* trn2 */, AArch64::TRN2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26813 { 6484 /* umulh */, AArch64::UMULH_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
26849 { 6517 /* uqadd */, AArch64::UQADD_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
27049 { 6687 /* uqsub */, AArch64::UQSUB_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
27252 { 6919 /* uzp1 */, AArch64::UZP1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
27267 { 6924 /* uzp2 */, AArch64::UZP2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
27373 { 7069 /* zip1 */, AArch64::ZIP1_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
27388 { 7074 /* zip2 */, AArch64::ZIP2_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },