reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
14114 { 1364 /* fmad */, AArch64::FMAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14255 { 1455 /* fmla */, AArch64::FMLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14286 { 1487 /* fmls */, AArch64::FMLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14342 { 1524 /* fmsb */, AArch64::FMSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14406 { 1551 /* fnmad */, AArch64::FNMAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14412 { 1564 /* fnmla */, AArch64::FNMLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14415 { 1570 /* fnmls */, AArch64::FNMLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 14418 { 1576 /* fnmsb */, AArch64::FNMSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16475 { 3328 /* mad */, AArch64::MAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16492 { 3343 /* mla */, AArch64::MLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16509 { 3347 /* mls */, AArch64::MLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16666 { 3397 /* msb */, AArch64::MSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21472 { 1364 /* fmad */, AArch64::FMAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21618 { 1455 /* fmla */, AArch64::FMLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21649 { 1487 /* fmls */, AArch64::FMLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21700 { 1524 /* fmsb */, AArch64::FMSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21764 { 1551 /* fnmad */, AArch64::FNMAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21770 { 1564 /* fnmla */, AArch64::FNMLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21773 { 1570 /* fnmls */, AArch64::FNMLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 21776 { 1576 /* fnmsb */, AArch64::FNMSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 23833 { 3328 /* mad */, AArch64::MAD_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 23854 { 3343 /* mla */, AArch64::MLA_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 23871 { 3347 /* mls */, AArch64::MLS_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 24024 { 3397 /* msb */, AArch64::MSB_ZPmZZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },