reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
14976 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15011 { 1868 /* ld1h */, AArch64::GLD1H_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15226 { 1957 /* ld1sh */, AArch64::GLD1SH_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15256 { 1963 /* ld1sw */, AArch64::GLD1SW_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15288 { 1969 /* ld1w */, AArch64::GLD1W_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15810 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15843 { 2464 /* ldff1h */, AArch64::GLDFF1H_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15910 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15936 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 15966 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 22334 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 22369 { 1868 /* ld1h */, AArch64::GLD1H_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 22584 { 1957 /* ld1sh */, AArch64::GLD1SH_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 22614 { 1963 /* ld1sw */, AArch64::GLD1SW_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 22646 { 1969 /* ld1w */, AArch64::GLD1W_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 23168 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 23201 { 2464 /* ldff1h */, AArch64::GLDFF1H_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 23268 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 23294 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, }, 23324 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_UXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW648, MCK__93_ }, },