reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
12721   { 25 /* add */, AArch64::ADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
17445   { 4576 /* sqadd */, AArch64::SQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
17863   { 5010 /* sqsub */, AArch64::SQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
18958   { 5924 /* sub */, AArch64::SUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
18994   { 5971 /* subr */, AArch64::SUBR_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
19492   { 6517 /* uqadd */, AArch64::UQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
19692   { 6687 /* uqsub */, AArch64::UQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
20079   { 25 /* add */, AArch64::ADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
24803   { 4576 /* sqadd */, AArch64::SQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
25221   { 5010 /* sqsub */, AArch64::SQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26316   { 5924 /* sub */, AArch64::SUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26352   { 5971 /* subr */, AArch64::SUBR_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26850   { 6517 /* uqadd */, AArch64::UQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
27050   { 6687 /* uqsub */, AArch64::UQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },