reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17003 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 17229 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 17758 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 17773 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 17837 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 17852 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 19632 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 19681 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 24361 { 3890 /* rshrnt */, AArch64::RSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 24587 { 4317 /* shrnt */, AArch64::SHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 25116 { 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 25131 { 4914 /* sqrshrunt */, AArch64::SQRSHRUNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 25195 { 4967 /* sqshrnt */, AArch64::SQSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 25210 { 5001 /* sqshrunt */, AArch64::SQSHRUNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 26990 { 6634 /* uqrshrnt */, AArch64::UQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, }, 27039 { 6679 /* uqshrnt */, AArch64::UQSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorHReg, MCK_Imm1_8 }, },