reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17924   { 5088 /* sri */, AArch64::SRI_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
17964   { 5111 /* srsra */, AArch64::SRSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
18005   { 5159 /* ssra */, AArch64::SSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
19772   { 6768 /* ursra */, AArch64::URSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
19827   { 6818 /* usra */, AArch64::USRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
25282   { 5088 /* sri */, AArch64::SRI_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
25322   { 5111 /* srsra */, AArch64::SRSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
25363   { 5159 /* ssra */, AArch64::SSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
27130   { 6768 /* ursra */, AArch64::URSRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },
27185   { 6818 /* usra */, AArch64::USRA_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg1_1__Imm1_81_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_Imm1_8 }, },