reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
13232   { 669 /* cmpeq */, AArch64::CMPEQ_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13243   { 675 /* cmpge */, AArch64::CMPGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13254   { 681 /* cmpgt */, AArch64::CMPGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13265   { 687 /* cmphi */, AArch64::CMPHI_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13276   { 693 /* cmphs */, AArch64::CMPHS_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13331   { 723 /* cmpne */, AArch64::CMPNE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13578   { 1048 /* facge */, AArch64::FACGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13589   { 1054 /* facgt */, AArch64::FACGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13684   { 1114 /* fcmeq */, AArch64::FCMEQ_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13719   { 1120 /* fcmge */, AArch64::FCMGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13754   { 1126 /* fcmgt */, AArch64::FCMGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13851   { 1150 /* fcmne */, AArch64::FCMNE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
13869   { 1167 /* fcmuo */, AArch64::FCMUO_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20590   { 669 /* cmpeq */, AArch64::CMPEQ_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20601   { 675 /* cmpge */, AArch64::CMPGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20612   { 681 /* cmpgt */, AArch64::CMPGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20623   { 687 /* cmphi */, AArch64::CMPHI_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20634   { 693 /* cmphs */, AArch64::CMPHS_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20689   { 723 /* cmpne */, AArch64::CMPNE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20941   { 1048 /* facge */, AArch64::FACGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20952   { 1054 /* facgt */, AArch64::FACGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21052   { 1114 /* fcmeq */, AArch64::FCMEQ_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21087   { 1120 /* fcmge */, AArch64::FCMGE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21122   { 1126 /* fcmgt */, AArch64::FCMGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21209   { 1150 /* fcmne */, AArch64::FCMNE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
21227   { 1167 /* fcmuo */, AArch64::FCMUO_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },