reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
13235   { 669 /* cmpeq */, AArch64::CMPEQ_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13246   { 675 /* cmpge */, AArch64::CMPGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13257   { 681 /* cmpgt */, AArch64::CMPGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13268   { 687 /* cmphi */, AArch64::CMPHI_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13279   { 693 /* cmphs */, AArch64::CMPHS_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13334   { 723 /* cmpne */, AArch64::CMPNE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13579   { 1048 /* facge */, AArch64::FACGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13590   { 1054 /* facgt */, AArch64::FACGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13685   { 1114 /* fcmeq */, AArch64::FCMEQ_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13720   { 1120 /* fcmge */, AArch64::FCMGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13755   { 1126 /* fcmgt */, AArch64::FCMGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13852   { 1150 /* fcmne */, AArch64::FCMNE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
13870   { 1167 /* fcmuo */, AArch64::FCMUO_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20593   { 669 /* cmpeq */, AArch64::CMPEQ_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20604   { 675 /* cmpge */, AArch64::CMPGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20615   { 681 /* cmpgt */, AArch64::CMPGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20626   { 687 /* cmphi */, AArch64::CMPHI_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20637   { 693 /* cmphs */, AArch64::CMPHS_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20692   { 723 /* cmpne */, AArch64::CMPNE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20942   { 1048 /* facge */, AArch64::FACGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20953   { 1054 /* facgt */, AArch64::FACGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21053   { 1114 /* fcmeq */, AArch64::FCMEQ_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21088   { 1120 /* fcmge */, AArch64::FCMGE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21123   { 1126 /* fcmgt */, AArch64::FCMGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21210   { 1150 /* fcmne */, AArch64::FCMNE_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
21228   { 1167 /* fcmuo */, AArch64::FCMUO_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5, AMFBS_HasSVE, { MCK_SVEPredicateDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },