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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc20137 { 77 /* addv */, AArch64::ADDVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
20139 { 77 /* addv */, AArch64::ADDVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR8, MCK_VectorReg64 }, },
21515 { 1395 /* fmaxnmv */, AArch64::FMAXNMVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
21532 { 1409 /* fmaxv */, AArch64::FMAXVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
21577 { 1435 /* fminnmv */, AArch64::FMINNMVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
21594 { 1449 /* fminv */, AArch64::FMINVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
24449 { 4041 /* saddlv */, AArch64::SADDLVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR32, MCK_VectorReg64 }, },
24451 { 4041 /* saddlv */, AArch64::SADDLVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR16, MCK_VectorReg64 }, },
24651 { 4430 /* smaxv */, AArch64::SMAXVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
24653 { 4430 /* smaxv */, AArch64::SMAXVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR8, MCK_VectorReg64 }, },
24685 { 4451 /* sminv */, AArch64::SMINVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
24687 { 4451 /* sminv */, AArch64::SMINVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR8, MCK_VectorReg64 }, },
26601 { 6280 /* uaddlv */, AArch64::UADDLVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR32, MCK_VectorReg64 }, },
26603 { 6280 /* uaddlv */, AArch64::UADDLVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR16, MCK_VectorReg64 }, },
26723 { 6388 /* umaxv */, AArch64::UMAXVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
26725 { 6388 /* umaxv */, AArch64::UMAXVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR8, MCK_VectorReg64 }, },
26756 { 6405 /* uminv */, AArch64::UMINVv4i16v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_4h, MCK_FPR16, MCK_VectorReg64 }, },
26758 { 6405 /* uminv */, AArch64::UMINVv8i8v, Convert__Reg1_1__VectorReg641_2, AMFBS_HasNEON, { MCK__DOT_8b, MCK_FPR8, MCK_VectorReg64 }, },