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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12778 { 77 /* addv */, AArch64::ADDVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
12780 { 77 /* addv */, AArch64::ADDVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
12781 { 77 /* addv */, AArch64::ADDVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },
14158 { 1395 /* fmaxnmv */, AArch64::FMAXNMVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
14161 { 1395 /* fmaxnmv */, AArch64::FMAXNMVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
14175 { 1409 /* fmaxv */, AArch64::FMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
14178 { 1409 /* fmaxv */, AArch64::FMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
14220 { 1435 /* fminnmv */, AArch64::FMINNMVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
14223 { 1435 /* fminnmv */, AArch64::FMINNMVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
14237 { 1449 /* fminv */, AArch64::FMINVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON_HasFullFP16, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
14240 { 1449 /* fminv */, AArch64::FMINVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
17090 { 4041 /* saddlv */, AArch64::SADDLVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_16b }, },
17092 { 4041 /* saddlv */, AArch64::SADDLVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_8h }, },
17094 { 4041 /* saddlv */, AArch64::SADDLVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_4s }, },
17293 { 4430 /* smaxv */, AArch64::SMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
17296 { 4430 /* smaxv */, AArch64::SMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
17299 { 4430 /* smaxv */, AArch64::SMAXVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },
17327 { 4451 /* sminv */, AArch64::SMINVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
17330 { 4451 /* sminv */, AArch64::SMINVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
17333 { 4451 /* sminv */, AArch64::SMINVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },
19242 { 6280 /* uaddlv */, AArch64::UADDLVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_16b }, },
19244 { 6280 /* uaddlv */, AArch64::UADDLVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_8h }, },
19246 { 6280 /* uaddlv */, AArch64::UADDLVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR64, MCK_VectorReg128, MCK__DOT_4s }, },
19365 { 6388 /* umaxv */, AArch64::UMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
19368 { 6388 /* umaxv */, AArch64::UMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
19371 { 6388 /* umaxv */, AArch64::UMAXVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },
19398 { 6405 /* uminv */, AArch64::UMINVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR16, MCK_VectorReg128, MCK__DOT_8h }, },
19401 { 6405 /* uminv */, AArch64::UMINVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR32, MCK_VectorReg128, MCK__DOT_4s }, },
19404 { 6405 /* uminv */, AArch64::UMINVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_FPR8, MCK_VectorReg128, MCK__DOT_16b }, },