reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17463 { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17470 { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17479 { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17502 { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17601 { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17608 { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17617 { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 17640 { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24821 { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24828 { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24837 { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24860 { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24959 { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24966 { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24975 { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, }, 24998 { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32 }, },