reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17465   { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17473   { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17482   { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17505   { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17603   { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17611   { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17620   { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
17643   { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24823   { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24831   { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24840   { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24863   { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24961   { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24969   { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
24978   { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },
25001   { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern }, },