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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc17467 { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17476 { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17485 { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17508 { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17605 { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17614 { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17623 { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
17646 { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24825 { 4589 /* sqdecb */, AArch64::SQDECB_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24834 { 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24843 { 4603 /* sqdech */, AArch64::SQDECH_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24866 { 4617 /* sqdecw */, AArch64::SQDECW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24963 { 4757 /* sqincb */, AArch64::SQINCB_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24972 { 4764 /* sqincd */, AArch64::SQINCD_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
24981 { 4771 /* sqinch */, AArch64::SQINCH_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },
25004 { 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4, AMFBS_HasSVE, { MCK_GPR64, MCK_GPR64as32, MCK_SVEPattern, MCK_mul, MCK_Imm1_16 }, },