reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
12840 { 129 /* andv */, AArch64::ANDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 13540 { 1001 /* eorv */, AArch64::EORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 13649 { 1089 /* faddv */, AArch64::FADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14162 { 1395 /* fmaxnmv */, AArch64::FMAXNMV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14179 { 1409 /* fmaxv */, AArch64::FMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14224 { 1435 /* fminnmv */, AArch64::FMINNMV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14241 { 1449 /* fminv */, AArch64::FMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14694 { 1842 /* lasta */, AArch64::LASTA_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14699 { 1842 /* lasta */, AArch64::LASTA_RPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_GPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14702 { 1848 /* lastb */, AArch64::LASTB_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 14707 { 1848 /* lastb */, AArch64::LASTB_RPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_GPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 16810 { 3504 /* orv */, AArch64::ORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 17297 { 4430 /* smaxv */, AArch64::SMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 17331 { 4451 /* sminv */, AArch64::SMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 19249 { 6287 /* uaddv */, AArch64::UADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 19369 { 6388 /* umaxv */, AArch64::UMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 19402 { 6405 /* uminv */, AArch64::UMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 20198 { 129 /* andv */, AArch64::ANDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 20898 { 1001 /* eorv */, AArch64::EORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 21007 { 1089 /* faddv */, AArch64::FADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 21520 { 1395 /* fmaxnmv */, AArch64::FMAXNMV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 21537 { 1409 /* fmaxv */, AArch64::FMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 21582 { 1435 /* fminnmv */, AArch64::FMINNMV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 21599 { 1449 /* fminv */, AArch64::FMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 22052 { 1842 /* lasta */, AArch64::LASTA_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 22057 { 1842 /* lasta */, AArch64::LASTA_RPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_GPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 22060 { 1848 /* lastb */, AArch64::LASTB_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 22065 { 1848 /* lastb */, AArch64::LASTB_RPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_GPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 24168 { 3504 /* orv */, AArch64::ORV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 24657 { 4430 /* smaxv */, AArch64::SMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 24691 { 4451 /* sminv */, AArch64::SMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 26607 { 6287 /* uaddv */, AArch64::UADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 26729 { 6388 /* umaxv */, AArch64::UMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, }, 26762 { 6405 /* uminv */, AArch64::UMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE, { MCK_FPR64, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorDReg }, },