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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12707 { 25 /* add */, AArch64::ADDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12711 { 25 /* add */, AArch64::ADDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
12766 { 72 /* adds */, AArch64::ADDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12770 { 72 /* adds */, AArch64::ADDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
12810 { 120 /* and */, AArch64::ANDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12812 { 120 /* and */, AArch64::ANDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
12831 { 124 /* ands */, AArch64::ANDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12833 { 124 /* ands */, AArch64::ANDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
12914 { 288 /* bic */, AArch64::BICWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12916 { 288 /* bic */, AArch64::BICXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
12943 { 292 /* bics */, AArch64::BICSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
12945 { 292 /* bics */, AArch64::BICSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
13493 { 971 /* eon */, AArch64::EONWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
13495 { 971 /* eon */, AArch64::EONXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
13503 { 975 /* eor */, AArch64::EORWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
13505 { 975 /* eor */, AArch64::EORXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
16760 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16762 { 3486 /* orn */, AArch64::ORNXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
16778 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16780 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
18944 { 5924 /* sub */, AArch64::SUBWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
18948 { 5924 /* sub */, AArch64::SUBXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
19000 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
19004 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20065 { 25 /* add */, AArch64::ADDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20069 { 25 /* add */, AArch64::ADDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20124 { 72 /* adds */, AArch64::ADDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20128 { 72 /* adds */, AArch64::ADDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20168 { 120 /* and */, AArch64::ANDWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20170 { 120 /* and */, AArch64::ANDXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20189 { 124 /* ands */, AArch64::ANDSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20191 { 124 /* ands */, AArch64::ANDSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20272 { 288 /* bic */, AArch64::BICWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20274 { 288 /* bic */, AArch64::BICXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20301 { 292 /* bics */, AArch64::BICSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20303 { 292 /* bics */, AArch64::BICSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20851 { 971 /* eon */, AArch64::EONWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20853 { 971 /* eon */, AArch64::EONXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
20861 { 975 /* eor */, AArch64::EORWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
20863 { 975 /* eor */, AArch64::EORXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24118 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
24120 { 3486 /* orn */, AArch64::ORNXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24136 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
24138 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
26302 { 5924 /* sub */, AArch64::SUBWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
26306 { 5924 /* sub */, AArch64::SUBXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
26358 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
26362 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },