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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14115 { 1369 /* fmadd */, AArch64::FMADDHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
14116 { 1369 /* fmadd */, AArch64::FMADDSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
14117 { 1369 /* fmadd */, AArch64::FMADDDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
14343 { 1529 /* fmsub */, AArch64::FMSUBHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
14344 { 1529 /* fmsub */, AArch64::FMSUBSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
14345 { 1529 /* fmsub */, AArch64::FMSUBDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
14407 { 1557 /* fnmadd */, AArch64::FNMADDHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
14408 { 1557 /* fnmadd */, AArch64::FNMADDSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
14409 { 1557 /* fnmadd */, AArch64::FNMADDDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
14419 { 1582 /* fnmsub */, AArch64::FNMSUBHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
14420 { 1582 /* fnmsub */, AArch64::FNMSUBSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
14421 { 1582 /* fnmsub */, AArch64::FNMSUBDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
16477 { 3332 /* madd */, AArch64::MADDWrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16478 { 3332 /* madd */, AArch64::MADDXrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
16671 { 3405 /* msub */, AArch64::MSUBWrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16672 { 3405 /* msub */, AArch64::MSUBXrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
17267 { 4412 /* smaddl */, AArch64::SMADDLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
17381 { 4523 /* smsubl */, AArch64::SMSUBLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
19339 { 6370 /* umaddl */, AArch64::UMADDLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
19451 { 6477 /* umsubl */, AArch64::UMSUBLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
21473 { 1369 /* fmadd */, AArch64::FMADDHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
21474 { 1369 /* fmadd */, AArch64::FMADDSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
21475 { 1369 /* fmadd */, AArch64::FMADDDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
21701 { 1529 /* fmsub */, AArch64::FMSUBHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
21702 { 1529 /* fmsub */, AArch64::FMSUBSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
21703 { 1529 /* fmsub */, AArch64::FMSUBDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
21765 { 1557 /* fnmadd */, AArch64::FNMADDHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
21766 { 1557 /* fnmadd */, AArch64::FNMADDSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
21767 { 1557 /* fnmadd */, AArch64::FNMADDDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
21777 { 1582 /* fnmsub */, AArch64::FNMSUBHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
21778 { 1582 /* fnmsub */, AArch64::FNMSUBSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
21779 { 1582 /* fnmsub */, AArch64::FNMSUBDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
23835 { 3332 /* madd */, AArch64::MADDWrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
23836 { 3332 /* madd */, AArch64::MADDXrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24029 { 3405 /* msub */, AArch64::MSUBWrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
24030 { 3405 /* msub */, AArch64::MSUBXrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24625 { 4412 /* smaddl */, AArch64::SMADDLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
24739 { 4523 /* smsubl */, AArch64::SMSUBLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
26697 { 6370 /* umaddl */, AArch64::UMADDLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },
26809 { 6477 /* umsubl */, AArch64::UMSUBLrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_GPR64, MCK_GPR32, MCK_GPR32, MCK_GPR64 }, },