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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13402 { 856 /* csel */, AArch64::CSELWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
13403 { 856 /* csel */, AArch64::CSELXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
13408 { 872 /* csinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
13409 { 872 /* csinc */, AArch64::CSINCXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
13410 { 878 /* csinv */, AArch64::CSINVWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
13411 { 878 /* csinv */, AArch64::CSINVXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
13412 { 884 /* csneg */, AArch64::CSNEGWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
13413 { 884 /* csneg */, AArch64::CSNEGXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
13874 { 1178 /* fcsel */, AArch64::FCSELHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_CondCode }, },
13875 { 1178 /* fcsel */, AArch64::FCSELSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_CondCode }, },
13876 { 1178 /* fcsel */, AArch64::FCSELDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_CondCode }, },
20760 { 856 /* csel */, AArch64::CSELWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20761 { 856 /* csel */, AArch64::CSELXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
20766 { 872 /* csinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20767 { 872 /* csinc */, AArch64::CSINCXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
20768 { 878 /* csinv */, AArch64::CSINVWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20769 { 878 /* csinv */, AArch64::CSINVXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
20770 { 884 /* csneg */, AArch64::CSNEGWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20771 { 884 /* csneg */, AArch64::CSNEGXr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_CondCode }, },
21232 { 1178 /* fcsel */, AArch64::FCSELHrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFullFP16, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_CondCode }, },
21233 { 1178 /* fcsel */, AArch64::FCSELSrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_CondCode }, },
21234 { 1178 /* fcsel */, AArch64::FCSELDrrr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_CondCode }, },