|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14028 { 1314 /* fcvtzs */, AArch64::FCVTZSs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
14030 { 1314 /* fcvtzs */, AArch64::FCVTZSSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
14031 { 1314 /* fcvtzs */, AArch64::FCVTZSSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
14032 { 1314 /* fcvtzs */, AArch64::FCVTZSSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
14063 { 1321 /* fcvtzu */, AArch64::FCVTZUs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
14065 { 1321 /* fcvtzu */, AArch64::FCVTZUSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
14066 { 1321 /* fcvtzu */, AArch64::FCVTZUSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
14067 { 1321 /* fcvtzu */, AArch64::FCVTZUSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
17131 { 4110 /* scvtf */, AArch64::SCVTFSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_FPR16, MCK_GPR32, MCK_Imm1_32 }, },
17133 { 4110 /* scvtf */, AArch64::SCVTFs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
17134 { 4110 /* scvtf */, AArch64::SCVTFSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_GPR32, MCK_Imm1_32 }, },
17137 { 4110 /* scvtf */, AArch64::SCVTFSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_GPR32, MCK_Imm1_32 }, },
17745 { 4850 /* sqrshrn */, AArch64::SQRSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
17760 { 4885 /* sqrshrun */, AArch64::SQRSHRUNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
17824 { 4944 /* sqshrn */, AArch64::SQSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
17839 { 4975 /* sqshrun */, AArch64::SQSHRUNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
19275 { 6325 /* ucvtf */, AArch64::UCVTFSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_FPR16, MCK_GPR32, MCK_Imm1_32 }, },
19277 { 6325 /* ucvtf */, AArch64::UCVTFs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
19278 { 6325 /* ucvtf */, AArch64::UCVTFSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_GPR32, MCK_Imm1_32 }, },
19281 { 6325 /* ucvtf */, AArch64::UCVTFSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_GPR32, MCK_Imm1_32 }, },
19619 { 6608 /* uqrshrn */, AArch64::UQRSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
19668 { 6656 /* uqshrn */, AArch64::UQSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
21391 { 1314 /* fcvtzs */, AArch64::FCVTZSs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
21393 { 1314 /* fcvtzs */, AArch64::FCVTZSSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
21394 { 1314 /* fcvtzs */, AArch64::FCVTZSSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
21395 { 1314 /* fcvtzs */, AArch64::FCVTZSSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
21426 { 1321 /* fcvtzu */, AArch64::FCVTZUs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
21428 { 1321 /* fcvtzu */, AArch64::FCVTZUSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_GPR32, MCK_FPR16, MCK_Imm1_32 }, },
21429 { 1321 /* fcvtzu */, AArch64::FCVTZUSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR32, MCK_Imm1_32 }, },
21430 { 1321 /* fcvtzu */, AArch64::FCVTZUSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_GPR32, MCK_FPR64, MCK_Imm1_32 }, },
24494 { 4110 /* scvtf */, AArch64::SCVTFSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_FPR16, MCK_GPR32, MCK_Imm1_32 }, },
24496 { 4110 /* scvtf */, AArch64::SCVTFs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
24497 { 4110 /* scvtf */, AArch64::SCVTFSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_GPR32, MCK_Imm1_32 }, },
24500 { 4110 /* scvtf */, AArch64::SCVTFSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_GPR32, MCK_Imm1_32 }, },
25103 { 4850 /* sqrshrn */, AArch64::SQRSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
25118 { 4885 /* sqrshrun */, AArch64::SQRSHRUNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
25182 { 4944 /* sqshrn */, AArch64::SQSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
25197 { 4975 /* sqshrun */, AArch64::SQSHRUNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
26638 { 6325 /* ucvtf */, AArch64::UCVTFSWHri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFullFP16, { MCK_FPR16, MCK_GPR32, MCK_Imm1_32 }, },
26640 { 6325 /* ucvtf */, AArch64::UCVTFs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR32, MCK_Imm1_32 }, },
26641 { 6325 /* ucvtf */, AArch64::UCVTFSWSri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR32, MCK_GPR32, MCK_Imm1_32 }, },
26644 { 6325 /* ucvtf */, AArch64::UCVTFSWDri, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasFPARMv8, { MCK_FPR64, MCK_GPR32, MCK_Imm1_32 }, },
26977 { 6608 /* uqrshrn */, AArch64::UQRSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },
27026 { 6656 /* uqshrn */, AArch64::UQSHRNs, Convert__Reg1_0__Reg1_1__Imm1_321_2, AMFBS_HasNEON, { MCK_FPR32, MCK_FPR64, MCK_Imm1_32 }, },