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definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 4823 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4825 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4827 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4829 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4831 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4833 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4835 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4837 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4839 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4841 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4843 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4845 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
6245 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
6247 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
6249 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
6251 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
6253 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
6255 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
6257 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
6259 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
6261 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
6263 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
6265 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
6267 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
6669 case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_:
7120 case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_: