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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 4123 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
4127 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
4133 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
4137 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
4159 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
4243 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4245 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4251 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4253 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4263 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4265 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4271 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4273 { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4315 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4317 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4703 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4705 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4707 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4709 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4711 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4713 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4715 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4717 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4719 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4721 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4723 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4725 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4727 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4729 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4731 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4733 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4735 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4737 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4739 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4741 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4743 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4745 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4747 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4749 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
6125 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
6127 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
6129 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
6131 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
6133 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
6135 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
6137 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
6139 { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
6141 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
6143 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
6145 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
6147 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
6149 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
6151 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
6153 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
6155 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
6157 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
6159 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
6161 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
6163 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
6165 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
6167 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
6169 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
6171 { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
6345 { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6353 { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6361 { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6369 { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6383 { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6391 { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6399 { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6407 { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6636 case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_:
7065 case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_: