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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12896 { 269 /* bdep */, AArch64::BDEP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12897 { 269 /* bdep */, AArch64::BDEP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12898 { 269 /* bdep */, AArch64::BDEP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12899 { 269 /* bdep */, AArch64::BDEP_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
12900 { 274 /* bext */, AArch64::BEXT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12901 { 274 /* bext */, AArch64::BEXT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12902 { 274 /* bext */, AArch64::BEXT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12903 { 274 /* bext */, AArch64::BEXT_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
12906 { 283 /* bgrp */, AArch64::BGRP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
12907 { 283 /* bgrp */, AArch64::BGRP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
12908 { 283 /* bgrp */, AArch64::BGRP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
12909 { 283 /* bgrp */, AArch64::BGRP_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
20254 { 269 /* bdep */, AArch64::BDEP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20255 { 269 /* bdep */, AArch64::BDEP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20256 { 269 /* bdep */, AArch64::BDEP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20257 { 269 /* bdep */, AArch64::BDEP_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
20258 { 274 /* bext */, AArch64::BEXT_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20259 { 274 /* bext */, AArch64::BEXT_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20260 { 274 /* bext */, AArch64::BEXT_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20261 { 274 /* bext */, AArch64::BEXT_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
20264 { 283 /* bgrp */, AArch64::BGRP_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVEVectorHReg }, },
20265 { 283 /* bgrp */, AArch64::BGRP_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEVectorSReg }, },
20266 { 283 /* bgrp */, AArch64::BGRP_ZZZ_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, },
20267 { 283 /* bgrp */, AArch64::BGRP_ZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2, AMFBS_HasSVE2BitPerm, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEVectorBReg }, },
27990 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
27991 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
27992 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
27993 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
27994 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
27995 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
27996 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },
27997 { 269 /* bdep */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },
27998 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
27999 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
28000 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
28001 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
28002 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
28003 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
28004 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },
28005 { 274 /* bext */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },
28006 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
28007 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE2BitPerm },
28008 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
28009 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorSReg, AMFBS_HasSVE2BitPerm },
28010 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
28011 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorDReg, AMFBS_HasSVE2BitPerm },
28012 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },
28013 { 283 /* bgrp */, 7 /* 0, 1, 2 */, MCK_SVEVectorBReg, AMFBS_HasSVE2BitPerm },